Reducing power dissipation of integrated circuits in battery-driven equipment, such as a cellular telephone or a personal digital assistant (PDA), is a significant challenge. Previously, static random access memories (SRAMs) have been used extensively in semiconductor memory applications, because a SRAM memory cell typically has six complementary metal oxide semiconductor (CMOS) transistors and allows data to be retained with a minimal amount of current drain. In terms of area, however, the SRAM memory cell, is larger than a DRAM memory cell by a factor of twenty or more. In addition, memory capacities are increasing proportionately with circuit and wiring densities. As such, fabricating a 32-Mbit or 64-Mbit SRAM using current wiring technology of about 0.2 μm to about 0.13 μm inevitably results in an excessively large chip. Consequently, from the viewpoint of area efficiency, SRAMs are inferior to DRAMs, and the disadvantage of poor area efficiency ultimately inhibits continued process technology scaling. For this reason, in many applications SRAMs are being replaced by DRAMs.
The DRAMs, however, require stored data to be refreshed, resulting in a considerably larger standby current than for SRAM arrays. To successfully replace SRAMs consuming less power with space-saving DRAMs, a trade-off is made between array density and stand-by power dissipation.
To solve the problem described above, a multi-chip package that combines a large-capacity DRAM and a small-capacity SRAM has been provided. The SRAM serves to back up the DRAM, and only the data that has to be retained among the data in the DRAM is stored in the SRAM. Even this product, however, has not achieved satisfactory reduction in power consumption.
According to a typical standard of DRAMs, a specified data retention rate is 64 ms. A memory controller is required to refresh each memory cell in a cycle bounded by the specified data retention rate. DRAM manufacturers conduct a “retention test” with sufficient margins to satisfy the aforementioned requirement and ship the products passing the test. The total number of memory cells exhibiting a retention rate with an extremely small margin is rather small compared to the number of cells in the array. Furthermore, memory cells having such short data retention rates usually exhibit one or more defects and are replaced by redundant memory cells and not actually used. Hence, the number of the memory cells with short data retention rates that are actually used is extremely small, as compared with the overall number of memory cells in the DRAM array under test.
Actual measurements of data retention time show that most DRAMs of any manufacturers exhibit long retention that easily exceeds the range of several seconds even at 85° C. For the retention test, an allowance is added to 64 ms to provide a reference value of, for example, 100 ms. For a given array, only a few dozen memory cells are incapable of exceeding the reference value. Typical distributions of data retention rates indicates that about 99% of the memory cells have data retention rates exceeding one second and an extremely small number of memory cells are distributed at the bottom where the data retention time is relatively short.
In a conventional DRAM, all memory cells are refreshed at the same interval, e.g., 64 ms, according to the standard, which ensures the shortest data retention rate of all memory cells is used for the refresh cycle. The study of the capability distribution of data retention rates described above reveals that the majority of memory cells are refreshed more frequently than necessary, wasting a considerable amount of power. Ideally, therefore, individual memory cells should be refreshed at intervals suited to the data retention rate capability of each memory cell. Thus, only a few dozen memory cells in a given array need refreshing at the shortest intervals of 64 ms, while the remaining majority of memory cells may be refreshed at intervals that are far longer, allowing considerable power to be saved. However, setting a refresh cycle based on the capability value of each memory cell would require a circuit of an enormous scale and complexity, rendering such a solution infeasible.
To solve the problem described above, an invention has been proposed in which memory cells are divided into groups and an optimum refresh cycle is set for each group. For instance, Japanese Unexamined Patent Application Publication No. 4-34794 discloses an invention in which an optimum refresh cycle is set for each word line. This invention, however, requires a circuit of an enormous scale and complexity to set different refresh cycles for numerous word lines. Japanese Unexamined Patent Application Publication No. 5-109268 discloses an invention in which an optimum refresh cycle is set for each subarray. Japanese Unexamined Patent Application Publication No. 5-266657 shown below has disclosed an invention in which an optimum refresh cycle is set for each memory cell array. In these inventions, however, the number of arrays is small, so that a satisfactory result cannot be obtained if memory cells having comparably short values of data retention rate are scattered among all arrays.